I am a Senior Deep Learning Performance Architect at NVIDIA, working on future hardware architectures and optimizations to advance the state-of-the-art in deep learning performance and energy-efficiency. Previously, I was a Machine Learning Engineer in Apple Neural Engine Compiler Team at Apple. I received my Ph.D. from CMU, co-advised by Prof. Diana Marculescu and Prof. Gauri Joshi. My dissertation was titled "Scalable and Efficient Systems for Deep Learning". Before joining CMU, I received my B.Sc. degree in Electronics Engineering at Sabanci University.

My research interests include Systems for ML, HW/SW Co-Design, and Efficient Deep Learning.

My Ph.D. research focused on designing scalable and efficient systems and ML models using HW/ML model co-design techniques to achieve the best of both worlds. I worked on quantization-aware DNN accelerator and model co-exploration through architecture-level modeling and efficient design space exploration. Before that, I worked on scalable and efficient reinforcement learning training on CPU-GPU systems. Additionally, my previous work has explored how to utilize emerging non-volatile memories in GPU architectures for DL workloads.